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| (R) CD4049UBMS Data Sheet March 6, 2007 FN3315.1 CMOS Hex Buffer/Converter The CD4049UBMS is an inverting hex buffer and features logic level conversion using only one supply (voltage (VCC). The input signal high level (VIH) can exceed the VCC supply voltage when this device is used for logic level conversions. This device is intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL 0.4V, and IOL 3.3mA. The CD4049UBMS is designated as replacement for CD4009UB. Because the CD4049UBMS requires only one power supply, it is preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB in all inverter, current driver, or logic level conversion applications. In these applications the CD4049UBMS is pin compatible with the CD4009UB, and can be substituted for this device in existing as well as in new designs. Terminal No. 16 is not connected internally on the CD4049UBMS, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink current or voltage conversion, the CD4069UB Hex Inverter is recommended. The CD4049UBMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP H4S H1E Features * High Voltage Type (20V Rating) * Inverting Type * High Sink Current for Driving 2 TTL Loads * High-to-Low Level Logic Conversion * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1mA at 18V Over Full Package Temperature Range; 100nA at 18V and +25C * 5V, 10V and 15V Parametric Ratings Applications * CMOS to DTL/TTL Hex Converter * CMOS Current "Sink" or "Source" Driver * CMOS High-to-Low Logic Level Converter Pinout CD4049UBMS TOP VIEW VCC G=A A H=B B I=C 1 2 3 4 5 6 7 8 16 NC 15 L = F 14 F 13 NC 12 K = E 11 E 10 J = D 9D Ceramic Flatpack H3X Functional Diagram A 3 2 G=A C VSS B 5 4 H=B Schematic VCC C 7 6 I=C D VCC VSS NC = 13 NC = 16 1 8 E 9 10 J=D P 11 12 K=E R IN N OUT F 14 15 L=F VSS FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CD4049UBMS Ordering Information PART NUMBER CD4049UBDMSR CD4049UBKMSR CD4049UBKNSR PART MARKING Q 5962R96 63601VEC Q 5962R96 63601VXC Q 5962R96 63602VXC TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 PACKAGE 16 Ld SBDIP, Solder Seal 16 Ld Flatpack, Solder Seal 16 Ld Flatpack, Solder Seal PKG. DWG. # D16.3 K16.A K16.A 2 FN3315.1 March 6, 2007 CD4049UBMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . -0.5V to 20.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range . . . . . . . . . . . . . . . .-55C to +125C Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . .-65C to +150C Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . +265C At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) Ceramic DIP and FRIT Package . . . . . 80 20 Flatpack Package. . . . . . . . . . . . . . . . . 70 20 Maximum Package Power Dissipation (PD) at +125C For TA = -55C to +100C (Package Type D, F, K) . . . . . .500mW For TA = +100C to +125C (Package Type D, F, K) . . . . . Derate Linearity at 12mW/C to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C DC Electrical Specifications PARAMETER Supply Current SYMBOL IDD CONDITIONS (Note 1) VDD = 20V, VIN = VDD or GND GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL4 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 4.5V, VOUT = 0.4V VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 1 7 7 8A 8B LIMITS TEMP (C) +25 +125 +55 +25 +125 -55 +25 +125 +55 +25, +125, -55 +25, +125, -55 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +125 -55 MIN -100 -1000 -100 14.95 2.6 3.2 8.0 24 -2.8 0.7 MAX 2 200 2 100 1000 100 50 -0.8 -3.2 -1.8 -6.0 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA mA V V V VOH > VDD/2 VOL < VDD/2 3 FN3315.1 March 6, 2007 CD4049UBMS DC Electrical Specifications PARAMETER Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. SYMBOL VIL VIH VIL VIH CONDITIONS (Note 1) VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMP (C) +25, +125, -55 +25, +125, -55 +25, +125, -55 +25, +125, -55 MIN 4.0 12.5 MAX 1.0 2.5 UNITS V V V V AC Electrical Specifications PARAMETER Propagation Delay SYMBOL tPHL CONDITIONS (Notes 4, 5) VDD = 5V, VIN = VDD or GND GROUP A SUBGROUPS 9 10, 11 Propagation Delay tPLH VDD = 5V, VIN = VDD or GND 9 10, 11 Transition Time tTHL VDD = 5V, VIN = VDD or GND 9 10, 11 Transition Time tTLH VDD = 5V, VIN = VDD or GND 9 10, 11 NOTES: 4. CL = 50pF, RL = 200k, Input tR, tF < 20ns. 5. -55C and +125C limits guaranteed, 100% testing being implemented. LIMITS TEMP (C) +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 MIN MAX 65 88 120 162 60 81 160 216 UNITS ns ns ns ns ns ns ns ns Post Irradiation Electrical Performance Characteristics LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 6, 7 TEMP (C) -55, +25 +125 VDD = 10V, VIN = VDD or GND 6, 7 -55, +25 +125 VDD = 15V, VIN = VDD or GND 6, 7 -55, +25 +125 Output Voltage Output Voltage Output Voltage Output Voltage VOL VOL VOH VOH VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load 6, 7 6, 7 6, 7 6, 7 +25, +125, -55 +25, +125, -55 +25, +125, -55 +25, +125, -55 MIN 4.95 9.95 MAX 1 30 2 60 2 120 50 50 UNITS A A A A A A mV mV V V 4 FN3315.1 March 6, 2007 CD4049UBMS Post Irradiation Electrical Performance Characteristics LIMITS PARAMETER Output Current (Sink) SYMBOL IOL4 CONDITIONS VDD = 4.5V, VOUT = 0.4V NOTES 6, 7 TEMP (C) +125 -55 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 6, 7 +125 -55 Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 6, 7 +125 -55 Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 6, 7 +125 -55 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 6, 7 +125 -55 Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 6, 7 +125 -55 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 6, 7 +125 -55 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 6, 7 +125 -55 Input Voltage Low Input Voltage High Propagation Delay VIL VIH tPHL VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VIN = 10V, VDD = 5V VIN = 10V, VDD = 10V Propagation Delay tPLH VIN = 10V, VDD = 5V VIN = 10V, VDD = 10V Propagation Delay tPHL VIN = 15V, VDD = 5V VIN = 15V, VDD = 15V Propagation Delay tPLH VIN = 15V, VDD = 5V VIN = 15V, VDD = 15V Transition Time tTHL VDD = 10V, VIN = VDD OR GND VDD = 15V, VIN = VDD OR GND Transition Time tTLH VDD = 10V, VIN = VDD OR GND VDD = 15V, VIN = VDD OR GND Input Capacitance NOTES: 6. All voltages referenced to device GND. 7. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 8. CL = 50pF, RL = 200k, Input tR, tF < 20ns. CIN Any Input 6, 7 6, 7 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7 +25, +125, -55 +25, +125, -55 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 MIN 1.8 3.3 2.4 4.0 5.6 10 18 26 8 MAX -0.48 -0.81 -1.55 -2.6 -1.18 -2.0 -3.1 -5.2 2 30 40 90 65 20 30 90 50 40 30 80 60 22.5 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns pF 5 FN3315.1 March 6, 2007 CD4049UBMS Post Irradiation Electrical Performance Characteristics LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTND VTP VTPD F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time NOTES: 9. All voltages referenced to device GND. 10. CL = 50pF, RL = 200k, Input tR, tF < 20ns. 11. See Table 2 for +25C limit. 12. Read and Record TABLE 1. BURN-IN AND LIFE TEST DELTA PARAMETERS +25C PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.2A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT tPHL tPLH VDD = 5V 9, 10, 11, 12 +25 1.35 x +25 Limit ns NOTES 9, 12 9, 12 9, 12 9, 12 9, 12 9 TEMP (C) +25 +25 +25 +25 +25 +25 MIN -2.8 0.2 MAX 7.5 -0.2 1 2.8 1 UNITS A V V V V V VOH > VDD/2 VOL < VDD/2 TABLE 2. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 13) Interim Test 3 (Post Burn-In) PDA (Note 13) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 13. 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A 6 FN3315.1 March 6, 2007 CD4049UBMS TABLE 3. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 4. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 14) Static Burn-In 2 (Note 14) Dynamic Burn-In (Note 16) Irradiation (Note 15) NOTES: 14. Each pin except pin 1, pin 16, and GND will have a series resistor of 10k 5%, VDD = 18V 0.5V 15. Each pin except pin 1, pin 16, and GND will have a series resistor of 47k 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 16. Each pin except pin 1, pin 16, and GND will have a series resistor of 4.75k 5%, VDD = 18V 0.5V OPEN 2, 4, 6, 10, 12, 13, 15 2, 4, 6, 10, 12, 13, 15 13 2, 4, 6, 10, 12, 13, 15, 16 GROUND 3, 5, 7-9, 11-14 8 8 8 VDD 1, 16 1, 3, 5, 7, 9, 11, 14, 16 1, 16 1, 3, 5, 7, 9, 11, 14 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 9V -0.5V 50kHz 25kHz Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25C SUPPLY VOLTAGE (VCC) = 5V OUTPUT VOLTAGE (VO) (V) 5 AMBIENT TEMPERATURE (TA) = +25C 70 15V 60 50 40 30 GATE-TO-SOURCE VOLTAGE (VGS) = 5V 20 10 10V 4 MINIMUM MAXIMUM 3 2 1 0 1 2 3 INPUT VOLTAGE (VI) (V) 4 0 1 2 3 4 5 6 7 8 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7 FN3315.1 March 6, 2007 CD4049UBMS Typical Performance Characteristics (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -8 OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25C 70 15V 60 50 40 30 -10V 20 GATE-TO-SOURCE VOLTAGE (VGS) = 5V 10 -35 -15V 0 1 2 3 4 5 6 7 8 -30 10V GATE-TO-SOURCE VOLTAGE (VGS) = 5V -10 -15 -20 -25 -7 -6 -5 -4 -3 -2 -1 0 -5 OUTPUT HIGH (SINK) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25C DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -8 -7 -6 -5 -4 -3 -2 -1 0 OUTPUT HIGH (SINK) CURRENT (IOH) (mA) 10 OUTPUT VOLTAGE (VO) (V) 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 +125C VCC = 5V -55C +125C SUPPLY VOLTAGE (VCC) = 10V AMBIENT TEMPERATURE (TA) = -55C AMBIENT TEMPERATURE (TA) = +25C -5 GATE-TO-SOURCE VOLTAGE (VGS) = 5V -10 -10V -15 -20 -25 -30 -35 -15V INPUT VOLTAGE (VI) (V) FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE 8 FN3315.1 March 6, 2007 CD4049UBMS Typical Performance Characteristics (Continued) POWER DISSIPATION PER INVERTER (mW) POWER DISSIPATION PER INVERTER (PD) (W) AMBIENT TEMPERATURE (TA) 8 = +25oC 6 4 2 SUPPLY VOLTAGE 104 (VDD) = 15V 8 6 4 10V 2 103 8 10V 6 4 5V 2 102 8 6 LOAD CAPACITANCE (CL) = 50pF 4 (11pF FIXTURE + 39pF EXT) 2 CL = 15pF (11pF FIXTURE + 4pF EXT 10 2 4 68 2 4 68 2 4 68 2 4 68 10 103 104 105 102 INPUT FREQUENCY (f) (kHz) 105 106 105 104 103 102 10 1 10 15V; 1MHz 15V; 100KHz 10V; 100KHz 15V; 10KHz 10V; 10KHz 15V; 1KHz SUPPLY VOLTAGE (VCC) = 5V FREQUENCY (f) = 10KHz 102 103 104 105 106 107 INPUT RISE AND FALL TIME (tr, tf) (ns) 108 AMBIENT TEMPERATURE (TA) = +25oC FIGURE 8. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS FIGURE 9. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kA - 14kA, PASSIVATION: 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches AL. 9 FN3315.1 March 6, 2007 CD4049UBMS Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C) 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94 E eA e eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 ccc M C A - B S D S aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN3315.1 March 6, 2007 CD4049UBMS Ceramic Metal Seal Flatpack Packages (Flatpack) A K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B) 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.245 0.130 0.030 0.008 0.250 0.026 0.005 16 MAX 0.115 0.022 0.019 0.009 0.006 0.440 0.285 0.315 0.015 0.370 0.045 0.0015 A b b1 c c1 D MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.22 3.30 0.76 1.27 BSC 0.20 6.35 0.66 0.13 16 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 11.18 7.24 8.00 NOTES 3 3 7 2 8 6 Rev. 1 2-20-95 e PIN NO. 1 ID AREA A -A- -B- D S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS E E1 E2 E3 e k L Q S1 M N 0.050 BSC BASE METAL b1 M M (b) SECTION A-A (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH 11 FN3315.1 March 6, 2007 |
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